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Home  >  Journal list  >  Journal of the Ceramic Society of Japan  >  Vol.117  No.1369 (September) (2009)  >  pp.1032-1034

Journal of the Ceramic Society of Japan
<<Previous article Vol.117  No.1369 (September) (2009)   pp.1032 - 1034 Next article>>

(Bi,La)4Ti3O12 as a ferroelectric layer and SrTa2O6 as a buffer layer for metal-ferroelectric-metal-insulator-semiconductor field-effect transistor

Joo-Nam KIM1), Yun-Soo CHOI2) and Byung-Eun PARK1)
1) School of Electrical and Computer Engineering, University of Seoul
2) Department of Geo-informatics, University of Seoul


  The metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) using the (Bi,La)4Ti3O12 (BLT) as a ferroelectric and SrTa2O6 (STA) as a buffer layer is prepared. The Au/STA/Si structure shows about 1 nF/cm2 of the accumulation capacitance value which is equivalent to about 6.2 nm of SiO2. The leakage current density is lower than 107 A/cm2 under 5 V. The remanent polarization of the 420 nm-thick BLT film was 35.2 μC/cm2 at 450 kV/cm. The MFMIS-FET was fabricated with different area ratio (AI/AF) from 1 to 8. From the drain current-gate voltage characteristics at the drain voltage of 0.2 V, the memory window is only 0.5 V for the device with AI/AF = 1 but it is increased to 1.8 V as the AI/AF is increased to 8. For the AI/AF ratio of 8, the "on" state of the drain current of 1.12 × 10-5 A rapidly drops after 105 s to 2 × 10-6 A and the "off" state current increase from 10-7 A to 10-6 A after 105 s. The on/off current ratio decrease from 3 × 102 to 8.


Keyword:
MFMIS structure, (Bi,La)4Ti3O12, SrTa2O6, FeRAM, Retention time

Received: October 30, 2008
Accepted: July 16, 2009 , Published online: September 01, 2009
Copyright (c) 2009 The Ceramic Society of Japan

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